verilog - How to increment 4 bit counter by 1 bit when a button is pressed -

i writing stop watch program on nexys4 fpga. can start, stop, , reset stopwatch, i'm having trouble implementing increment feature. increment feature button, when pressed, increment clock 1 millisecond. if 7 segment display showing 1:002 , increment button pressed, display show 1:003. here snippet of code counter:

always @ (posedge (clk), posedge(rst)) begin    if (rst == 1'b1)begin         dig0 <= 4'b0000;         dig1 <= 4'b0000;         dig2 <= 4'b0000;         dig3 <= 4'b0000;     end   //increment if inc else if(state == 2'b11)// && dig3 < 4'b1001)begin begin     dig0 <= dig0 + 4'b0001;     state <= 2'b00; end   //only continue if cen 01 & not inc else if(cen == 2'b01)begin        //add 1 first digit till 9     dig0 <= dig0 + 1'b1;      //reset if == 10             if(dig0 > 4'b1001)begin             dig0 <= 4'b0000;              //add 1 second digit (when first resets) till 9             dig1 <= dig1 + 1'b1;             end             //reset if == 10             if(dig1 == 4'b1010)begin                 dig1 <= 4'b0000;                  //add 1 third digit (when second reset) till 9                 dig2 <= dig2 + 1'b1;                 end                 //reset if == 10                 if(dig2 == 4'b1010)begin                     dig2 <= 4'b0000;                      //add 1 fourth digit (when third reset) till 9                     dig3 <= dig3 + 1'b1;                     end                     //reset if == 10                     if(dig3 > 4'b1001)begin                         dig3 <= 4'b0000;                      end              end  

cen coming state machine state 2'b11 increment, 2'b01 count, , 2'b00 stop. can't figure out how increment 1 bit. whenever hit increment counts forever. ideas?

thanks

without state-machine code can make guess problem . need post state-machine code conform guess.

but probable reason counter continuing increment cen high (2'b01) while state 2'b11.

cycle 1 ) - state == 2'b11 , cen == 2'b01              dig0 +1 , state = 0   cycle 2 )  - state = 0 , cen == 2'b01                goes else clause , counter continues increment                long cen 2'b01 

there few issue may need fix .

1) in increment section (state = 2'b11 ) still need check , increment 4 digits ( dig0-3 ) incrementing dig0 ( more 9 times ) result in roll on next digit , on.

2) better update state machine variables in single block. better move statement state = 2'b0 state-machine.

3) suggested in comments have single counter , decode digits.