assembly - Did I translate the very short C code correctly into assembler? -
i'm learning assembly x86 , have made little task myself.
the c code:
if (a == 4711) { = + 2 } else { = - 2 }
assembler code (eax
register, cmp
compare, jne
jump if not equal , jmp
jump if equal):
mov eax, cmp eax, 4711 jmp equal equal: add eax, 2 jne unequal unequal: sub eax, 2
i think little more efficient be:
mov eax, cmp eax, 4711 jne unequal add eax, 2 unequal: sub eax, 2
edit:
mov eax, cmp eax, 4711 jne unequal equal: add eax, 2 jmp continue unequal: sub eax, 2 continue: ...
did translate correctly?
let's first code:
mov eax, cmp eax, 4711 jmp equal equal: add eax, 2 jne unequal unequal: sub eax, 2
let's pretend first instruction load eax
"a" (it in tasm/masm, rather stick explicit , accurate [a]
, it's easier read source , works in nasm).
second instruction cmp
, subtract 4711 eax, throws result away (not storing anywhere), , flag register affected. if "a" 4711, result of subtraction zero, zf=1 then. otherwise zf=0. (for other flags affected cmp see documentation).
so on line 3 eax
still contains value "a", , flag register contains result of cmp eax,4711
. , jmp
. unconditional jump, happening no matter what, directly continue instruction @ "equal" address, add eax,2
. => add 2 "a" in every case.
also add
affects flags, "a" == -2 zf=1, otherwise zf=0!
then comes first conditional jump, branching code, based on current flag register content. jne
abbreviation of "jump not equal", , "equal" in context means set 0 flag (zf=1).
so when "a" -2, zf 1 ("is equal") ahead of jne
, jne
not jump "unequal" address, continue next instruction (which @ "unequal" address anyway, jne
meaningless).
for "a" different -2 zf 0 ("is not equal"), jne
execute jump on provided label, continuing instruction @ address "unequal".
so have navigate cpu away instructions don't want execute.
xor eax,eax ; sets eax 0, , zf=1 jz label_1 ; zf 1, jump executed, cpu goes "label_1" inc eax ; instruction skipped , not executed label_1: ; eax being still 0, , zf being still set on ; whatever instruction here, cpu execute after "jz"
slightly modified example show case when condition false
xor eax,eax ; sets eax 0, , cf=0, zf=1, ... jc label_1 ; cf 0, "jump carry" not executed inc eax ; instruction executed after "jc" label_1: ; here eax 1 ; cf still 0 (not affected inc) ; zf 0 (affected inc)
summary: should have pretty idea instructions affect flags, , in way. when unsure, keep cmp
+ jcc
pair (to not affect flag results cmp
accidentally). jcc
stands "conditional jump" instruction. when condition met, jump provided label executed. otherwise jcc
instruction ignored, , execution continue instruction right after it.
btw, write c code:
if (a == 4711) { = + 2 } else { = - 2 }
as:
cmp [a],dword 4711 mov eax,2 je a_is_4711 neg eax ; -2 non 4711 value a_is_4711: add [a],eax
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